1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor wafers. More specifically, the present invention relates to an integrated alignment and overlay pattern for determining the registration accuracy between two patterned layers on a semiconductor wafer.
2. Description of the Prior Art
As known in the art, lithographic process is an essential step that determines the feature critical dimension (CD) in the manufacture of semiconductor integrated circuit device. Ordinarily, electric circuit patterns are formed by first transferring the pattern on a photo mask to a photoresist layer in a lithographic process, and then transferring the pattern from the photoresist layer to an underlying material layer such as a dielectric layer or a metal layer in a subsequent etching process.
In order to increase production yield, alignment and overlay marks are typically provided on a wafer. By way of example, a sample wafer with alignment marks is put into product lines for testing alignment accuracy before wafers are practically in mass production. In the lithography process, the photo mask and the wafer are first aligned by an exposure tool using a set of pre-layer alignment marks typically located on a scribe line of the wafer. Then, the exposure tool detects the alignment marks and the reflected light signal is analyzed by the exposure tool to obtain precise alignment prior to the actual exposure process. The alignment mark typically includes a set of trenches etched into a material layer on a wafer.
After exposure, the photoresist layer on the wafer is then subjected to development process to form a photoresist pattern. Before implementing the etching process for transferring the photoresist pattern into the underlying material layer, it is important to check if the electric circuit feature defined in the developed photoresist layer perfectly matches with the electric circuit pattern previously formed on the wafer. The post-development accuracy of the alignment is evaluated in an overlay tool by taking overlay marks on a wafer as an overlay reference. The overlay mark, which is located in an area other than the alignment mark region, typically comprises a pre-layer pattern and a current-layer pattern arranged in a box-in-box configuration. The offset between a pre-layer pattern and the current-layer pattern can be measured by the overlay tool, and the exposure parameters can be adjusted with the feedback of the overlay alignment data from the overlay tool.
However, the above-described prior art has drawbacks. Since the alignment mark and overlay mark are respectively measured by different tools, i.e. the exposure tool and the overlay tool, the wafer stages and the detectors in each tool all have their own deviations. In other words, the measured results obtained from a single tool become more complicated due to the addition of the respective deviations and the total deviations become adversely enhanced. In addition, the overlay mark and the alignment mark region are located in different regions of a wafer. The separated alignment mark and overlay mark occupy valuable chip area and is thus not area efficient.